1. Field of the Invention
This invention relates to interconnection matrixes for circuit routing in Integrated Circuit (IC). In particular, an array of semiconductor NVM devices is applied to form an interconnection matrix. Applied with a control gate voltage bias lower than the high threshold voltage and higher than the low threshold voltage, the NVM devices with programmed high threshold voltages are “off” to disconnect the two input-output terminals. While the un-programmed NVM devices with low threshold voltages having the same applied control gate bias are “on” to connect the two input-output terminals.
2. Description of the Related Art
In field of Integrated Circuit (IC), active elements like transistors and passive elements like resistors and capacitors are connected by metal wires and inter-layered metal vias/contacts. The metal connection is usually done by the final metallization process in semiconductor manufacturing. Once the final hard wiring process is completed the circuitry is not able to change without re-masking and re-processing on the new silicon. Lack of flexibility of changing the wiring configuration after fabrication the hard wiring methodology usually results in the development cost increase for mask revision and silicon re-fabrication, and further prolongs the development time.
In most IC chips, minor wiring changes after manufacturing process are necessarily required for trimming the electrical parameters of passive elements, memory redundancy for yield improvement, and chip identifications. For such applications, electrical fuses and anti-fuses are usually used for those purposes. Once programmed, the electrical fuses (anti-fuses) cannot convert back to their original state, that is, the programmed states of fuses (anti-fuses) are not reversible. For the reason, the electrical fuses (anti-fuses) are One-Time-Programmable (OTP) non-volatile memory elements.
On the other hand, OTP types of fuses (anti-fuses) are not able to provide viable solutions for the applications requiring large configurable wiring capacity such as Field Programmable Array (FPA) and multiple configurable I/Os (input/output pads). Using large amounts of OTP fuses (anti-fuses) for the multiple times configurable wiring capacity in IC chips become unrealistic costly. Since the semiconductor non-volatile memory devices are usually required to provide at least ten thousand times of programming-erase cycling the choice of non-volatile memories with Multiple Times Programmable (MTP) capability would be the most cost effective solution for multiple times wiring configurations in IC chips.
Semiconductor non-volatile memory is a type of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) capable of storing charges to alter the threshold voltages of the MOSFET. For example, electrons stored in the storing material of the semiconductor non-volatile memory cause the threshold voltage of the MOSFET shifted to a higher threshold voltage. The threshold voltage of the semiconductor non-volatile memory is shifted down to a lower threshold voltage after removing the stored electrons from the storing material or injection of holes to neutralize the stored electrons. The programming process is to raise the threshold voltage of a semiconductor non-volatile memory to a higher threshold voltage state while the erase process is to lower a programmed non-volatile memory from a high threshold voltage state to a low threshold voltage state. The programming/erase methods such as Hot Carrier Injection (HCI), Fowler-Nordheim (FN) tunneling, and Band-to-Band (BTB) tunneling for semiconductor non-volatile memory are well-known in the field. Since the stored charges in the storing material of a semiconductor non-volatile memory can be held for a long period of time for at least ten years under normal operational condition the threshold voltage of the non-volatile MOSFET remains insignificant changes during the course of operations. The “on”/“off” characteristics of semiconductor non-volatile memory will retain through the operational life for at least ten years.
Another aspect of applying semiconductor non-volatile memory for interconnection matrix in IC chip is that the core operational voltages in modern IC chips have been reduced to 1 volt more or less. The core operational voltage can be easily passed by semiconductor non-volatile memory devices without applying too high voltages to their control gates. Furthermore, the low core operational voltages of the modern IC chips are coincident with the required low voltages for applying to the drain electrodes of non-volatile memory devices without disturbing the devices' threshold voltages from the drain hot carrier injection, a phenomenon known as the read disturbance from applying high drain voltages.
In another aspect of applying semiconductor non-volatile memory for interconnection matrix in IC chips, a Scalable Gate Logic Non-Volatile Memory (SGLNVM) using standard CMOS process has been successfully developed (U.S. patent application Ser. Nos. 13/399,753 and 13/454,871, the disclosures of which are incorporated herein by reference in their entirety). SGLNVM is easily incorporated in the standard CMOS IC manufacturing with no added process cost. Owing to the non-volatile “on”/“off” and MTP properties of SGLNVM, the SGLNVM interconnection matrix can provide a very convenient and cost effective mean for configuring circuit routings in IC chips.